IEC 61691-5-2004 (IEEE 1076.4) PDF

Full title and description

Behavioural languages — Part 5: VITAL ASIC (application specific integrated circuit) modeling specification. This is the IEC/IEEE double‑logo publication corresponding to IEEE Std 1076.4 (VITAL), providing a standardized VHDL‑based methodology for modelling ASIC components to support efficient, accurate, and tool‑independent simulation of large chip‑level designs.

Abstract

The standard defines the VITAL (VHDL Initiative Toward ASIC Libraries) modeling specification: language constructs, timing and delay modelling, backannotation mechanisms, predefined primitives and tables, memory function and timing specifications, and package definitions that enable portable, high‑performance gate‑level and library models for ASICs. It was produced as a joint IEEE/IEC effort to harmonize VHDL‑based ASIC modeling for EDA tool interoperability.

General information

• Status: Withdrawn (IEC withdrawal completed in 2010; IEEE edition is inactive/withdrawn).
• Publication date: 7 October 2004 (IEC ed. 1.0).
• Publisher: International Electrotechnical Commission (IEC) / Institute of Electrical and Electronics Engineers (IEEE) — double‑logo international standard.
• ICS / categories: 25.040.01; 35.060.
• Edition / version: Edition 1.0 (2004).
• Number of pages: 430 pages (IEC publication metadata).

Scope

Provides a standard method for modelling application‑specific integrated circuits (ASICs) in VHDL to support accurate and efficient simulation at chip level. The scope includes language elements and model levels (Level 0 and Level 1), delay and timing specification, backannotation, predefined primitives and tables, and memory timing and functional models to enable portable, tool‑independent ASIC library models. The specification was intended primarily for gate‑level and post‑layout simulation and library exchange.

Key topics and requirements

• VITAL modeling methodology and conventions (Level 0 and Level 1 model definitions).
• Timing and delay modelling, including selection and backannotation mechanisms.
• Predefined primitives, tables, and syntax summaries to support efficient simulation.
• Memory function and timing specifications for modelling ASIC memories.
• Standard packages and glossary to promote model portability across EDA tools.

Typical use and users

Primary users include ASIC vendors, IP/library providers, EDA tool developers, verification and simulation engineers, and design teams needing gate‑level or library models for timing verification and signoff simulations. Historically important in ASIC flows and vendor library distributions; today it is more commonly found in legacy flows or when interoperating with older toolchains.

Related standards

Closely related to IEEE Std 1076 (VHDL language reference), IEEE Std 1164 (multi‑valued logic packages), IEC/IEEE 61691‑1‑1 (VHDL language reference manual), and other parts of the IEC 61691 behavioural languages series (e.g., VHDL‑AMS parts). VITAL complements VHDL core language standards by specifying ASIC‑oriented modelling conventions.

Keywords

VITAL, VHDL, ASIC modelling, gate‑level simulation, backannotation, timing, Level 0, Level 1, memory timing, IEEE 1076.4, IEC 61691‑5:2004.

FAQ

Q: What is this standard?

A: IEC/IEEE 61691‑5:2004 (IEEE Std 1076.4) is the VITAL ASIC modeling specification — a VHDL‑based standard that defines conventions and constructs for producing portable, efficient ASIC and library models for simulation.

Q: What does it cover?

A: It covers model levels (Level 0/Level 1), timing and delay formats, backannotation, predefined primitives/tables, memory modelling, standard packages and syntax summaries needed to build high‑performance gate‑level and library models for ASIC simulation.

Q: Who typically uses it?

A: ASIC/IP vendors, EDA tool vendors, simulation and verification engineers, and any organisation distributing or consuming VHDL‑based ASIC libraries and gate‑level simulation models. It saw most use in ASIC flows and library exchange.

Q: Is it current or superseded?

A: The IEC edition (61691‑5:2004) and the IEEE counterpart (1076.4) are listed as withdrawn/inactive. IEC records show a withdrawal date in 2010; the IEEE record for the 1076.4 edition is listed inactive/withdrawn. Users should treat the specification as legacy and verify current toolchain support or newer recommended practices for new projects.

Q: Is it part of a series?

A: Yes — it is Part 5 of the IEC/IEEE 61691 series (Behavioural languages). Other parts cover the VHDL language reference, multi‑value logic (1164), VHDL‑AMS, and related language packages and utilities.

Q: What are the key keywords?

A: VITAL, VHDL, ASIC modelling, gate‑level simulation, timing/backannotation, memory timing, IEEE 1076.4, IEC 61691‑5.