IEEE Std 1012-2016 PDF

Full title and description

IEEE Standard for System, Software, and Hardware Verification and Validation — IEEE Std 1012-2016. A process standard that defines verification and validation (V&V) life‑cycle processes, minimum V&V tasks by integrity level, required inputs and outputs, and the content of Verification and Validation Plans for systems, software (including firmware and microcode), and hardware (including COTS and reused items), including their interfaces and related documentation.

Abstract

This standard specifies V&V processes used to determine whether development products conform to their requirements and satisfy intended use and user needs. It covers analysis, evaluation, review, inspection, assessment, and testing activities across the life cycle and maps minimum V&V tasks to a four‑level integrity schema. IEEE Std 1012-2016 provides a common framework for planning and executing verification and validation for systems, software, and hardware.

General information

• Status: Superseded standard (superseded by IEEE 1012-2024).
• Publication date: Published / approved 29 September 2017 (designated 2016 edition).
• Publisher: IEEE (IEEE Computer Society / IEEE Standards Association).
• ICS / categories: Software development and system documentation (ICS 35.080 — software/systems engineering).
• Edition / version: IEEE Std 1012-2016 (with corrigendum incorporated at publication).
• Number of pages: 260 pages (published product listing).

Scope

Applies to verification and validation of systems, software (including firmware and microcode), and hardware throughout development, maintenance, and reuse (including legacy and commercial off‑the‑shelf items). The standard is life‑cycle agnostic (compatible with multiple life‑cycle models) and covers V&V activities for Agreement, Organizational Project‑Enabling, Project, Technical, Implementation, Support, and Reuse process groups; it addresses interfaces and documentation as part of the system of interest.

Key topics and requirements

• Establishes a common V&V framework and terminology for systems, software, and hardware.
• Defines minimum V&V tasks and required inputs/outputs mapped to a four‑level integrity (criticality) schema.
• Specifies content and tailoring guidance for the Verification and Validation Plan (SVVP).
• Covers V&V techniques and activities: analysis, reviews/inspections, assessments, and testing (unit, integration, qualification, regression, etc.).
• Addresses V&V for reused, legacy, and COTS components and the treatment of interfaces and documentation.
• Includes considerations for independent V&V (IV&V) and organizational tailoring to project constraints.

Typical use and users

Used by systems engineers, software engineers, V&V/test teams, quality assurance and configuration managers, project managers, and independent V&V organizations. Commonly applied in regulated or high‑integrity domains (aerospace/defense, transportation, medical devices, critical infrastructure) and any project requiring a formalized V&V approach tied to integrity levels.

Related standards

Closely related to and commonly used alongside lifecycle and testing standards such as ISO/IEC/IEEE 12207 (software life‑cycle processes) and ISO/IEC/IEEE 15288 (system life‑cycle processes), software testing standards (ISO/IEC/IEEE 29119 series), and systems/software engineering vocabulary and guidance standards (e.g., ISO/IEC/IEEE 24765). IEEE 1012 has earlier editions (e.g., 2012, 2004) and is followed by the updated IEEE 1012-2024.

Keywords

verification and validation, V&V, IV&V, verification tasks, validation activities, integrity levels, verification plan, verification and validation plan (SVVP), testing, inspection, review, system V&V, software V&V, hardware V&V, COTS, firmware, lifecycle processes.

FAQ

Q: What is this standard?

A: IEEE Std 1012-2016 is the IEEE Standard for System, Software, and Hardware Verification and Validation that defines V&V processes, minimum tasks by integrity level, and the content of V&V plans across system/software/hardware life cycles.

Q: What does it cover?

A: It covers planning and execution of verification and validation activities (analysis, reviews/inspections, assessments, and testing), mapping of minimum tasks to integrity levels, treatment of reused/COTS/firmware items, and V&V inputs/outputs for life‑cycle process groups.

Q: Who typically uses it?

A: Systems and software engineers, V&V/test teams, QA and configuration managers, project managers, and independent V&V organizations — especially in high‑integrity or safety‑critical domains.

Q: Is it current or superseded?

A: IEEE Std 1012-2016 has been superseded; the active/superseding revision is IEEE 1012-2024. The 2016 edition was published/approved on 29 September 2017 and includes corrigendum items incorporated at publication.

Q: Is it part of a series?

A: Yes — it is part of the IEEE software/systems engineering standards family and has prior editions (1986, 1998, 2004, 2012) and subsequent revisions; it is also used alongside international lifecycle and testing standards (ISO/IEC/IEEE 12207, 15288, 29119, etc.).

Q: What are the key keywords?

A: Verification and validation (V&V), independent V&V (IV&V), integrity level, verification tasks, validation activities, V&V plan, testing, review, inspection, systems engineering.