TDS PDF

2.5 V BiCMOS Logic Device Family Specification with 5 V Tolerant Inputs and Outputs. Original standard EIA JEDEC JESD70-1999 in PDF full version. Additional info + preview on request

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Standard Test and Programming Language (STAPL). Original standard EIA JEDEC JESD71-1999 in PDF full version. Additional info + preview on request

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Description of 5 V Bus Switch Devices with TTL-Compatible Control Inputs. Original standard EIA JEDEC JESD73-1999 in PDF full version. Additional info + preview on request

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High Speed Transceiver Logic (HSTL) – A 1.5 V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits. Original standard EIA JEDEC JESD8-6-1995 in PDF full version. Additional info + preview on request

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Stub Series Terminated Logic for 3.3 Volts (SSTL_3). Original standard EIA JEDEC JESD8-8-1996 in PDF full version. Additional info + preview on request

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Air-Convection-Cooled Life Test Environment for Lead-Mounted Semiconductor Devices. Original standard EIA RS-323-1966 (1972) in PDF full version. Additional info + preview on request

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