Turkmenistan standards PDF

Guideline for Characterizing Solder Bump Electromigration under Constant Current and Temperature Stress. Original document JEDEC JEP154A.01-2025 in PDF full version. Additional info + preview on request

Document status: Active

Recommended ESD Target Level for HBM Qualification. Original document JEDEC JEP155B-2018 in PDF full version. Additional info + preview on request

Document status: Active

Chip-Package Interaction Understanding, Identification, and Evaluation. Original document JEDEC JEP156A-2018 in PDF full version. Additional info + preview on request

Document status: Active

Recommended ESD-CDM Target Levels. Original document JEDEC JEP157A-2022 in PDF full version. Additional info + preview on request

Document status: Active

3D Chip Stack with Through-Silicon Vias (TSVs)- Identifying, Evaluating and Understanding Reliability Interactions. Original document JEDEC JEP158-2009 in PDF full version. Additional info + preview on request

Document status: Replaced by

Procedure for the Evaluation of Low-k/Metal Inter/Intra-Level Dielectric Integrity. Original document JEDEC JEP159A-2015 in PDF full version. Additional info + preview on request

Document status: Active